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ASIC DRAM Bus and PDN Designer
North American Production Sharing de México, S.A. de C.V.
Tijuana, Baja California
Enero 19 2026
Compartir:
Corporativo
Giro
Maquiladora (Export.)
Actividad principal
Administración de maquiladoras.
Número de empleados
10000
Sitio Web corporativo
Descripción y detalle de las actividades
As a leading technology innovator, we push the boundaries of what's possible and drive transformation in communication and data processing to help create a smarter, connected future for all. In this journey, we are evolving into an “AI-first” intelligent-edge powerhouse, combining high-performance, low-power compute and seamless connectivity while pushing intelligence closer to users through ultra-efficient, on-device AI that ensures privacy, personalization, and real-time responsiveness. This is the Invention Age—and this is where you come in.
Key Responsibilities:
- Work with system architecture and SoC design teams, define and assess 3DIC process technology requirements and roadmap.
- PPAC assessment for System-Technology Co-Optimization (STCO) for new product development.
- Foundry interface for 3DIC physical design flow and key design rule definitions.
- Establish dependency of 3D process solutions on key chip architecture and design KPI and co-optimize 3D solutions accordingly.
- Pathfinding and development of chiplet physical design methodology and PDK development.
- 3D DRAM and Cache SRAM Architecture evaluation for AI and other Compute workloads.
- Custom DRAM integration technology evaluation and pathfinding.
Experiencia y requisitos
Desired Skillset/Experience:
- Experience with 2.5D and 3D STCO and pathfinding.
- 2.5 and 3D Chip partition and dependencies on Product KPI like performance, power, chip and beachfront area, chip-chip communication metrics, power grid, etc.
- System and/or chip-level architecture and physical design experience for 3D cache partitioning (a plus).
- Physical design experience with SoIC and/or CoWoS.
- Experience with 2.5D/3D IC design flow and PDK development.
- Familiarity with heterogeneous integration processes such as hybrid bonding, wafer bonding, TSV, backside metallization.
- Process development and/or system and product development experience with advanced technology (sub 4nm) and its PPAC assessment.
- Custom layout, svrf, scripting skills.
- Hands-on experience with DRC, LVS, PEX (a plus).
- Ability to work across teams and BUs.
- Ability to work without supervision and as part of a team.
- Most tasks do not have defined steps; simultaneous use of multiple mental abilities is generally required to determine the best approach.
- Advanced data analysis and interpretation skills are required.
Education:
- Bachelor's degree in science, Engineering, or related field and 5+ years of AI relevant System and technology or related work experience.
- OR master's degree in science, Engineering, or related field and 4+ years of AI relevant System and technology or related work experience.
- OR PhD in Science, Engineering, or related field and 3+ years of AI relevant System and technology or related work experience.
Beneficios
Número de vacantes 1
Área Ingeniería
Contrato Permanente
Modalidad Presencial
Turno Diurno
Jornada Tiempo Completo
Horario
- Tiempo completo
Estudios Carrera con título profesional
Inglés Hablado: Avanzado, Escrito: Avanzado
Disponibilidad p. viajar No