Diseñador de procesadores (Semiconductors)

Join our growing international team as a Standard Cell Layout Designer—no prior industry experience required. We’re looking for candidates with strong academic foundations, excellent attention to detail, and a desire to learn cutting‑edge technologies.

As a Standard Cell Layout Designer, you will work with highly standardized layout blocks—the “lego pieces” of digital CMOS circuit libraries. Your main responsibility is to assemble and optimize these blocks according to strict design rules so that every cell fits together perfectly, without gaps or mismatches.

This team differs from custom analog layout groups: the focus is on systematic, rule-based work, precision, and layout consistency across large-scale libraries used in advanced semiconductor technologies.

You will work closely with global engineering teams, follow detailed specifications, and grow your skills in layout methodologies, CAD tools, scripting, and advanced semiconductor nodes.

What You’ll Do

• Build and integrate standard cell layout blocks using strict design rules to ensure perfect alignment and seamless cell boundaries.
• Apply systematic layout methodologies to create scalable, uniform, reproducible designs.
• Use industry-standard tools such as Cadence and Calibre for layout creation and verification.
• Maintain and organize layout databases using specialized design management systems.
• Collaborate with a global team to align on design rules, quality expectations, and delivery timelines.
• Troubleshoot design issues, interpret specifications, and produce layout that meets process, electrical, and physical requirements.
• Learn and follow internal methodologies for standard cell architecture and advanced-node processes.
• Track design progress, document updates, and communicate effectively with team leads.