North American Production Sharing de México, S.A. de C.V.

Entry Level Digital Design Engineer (Semiconductors)

North American Production Sharing de México, S.A. de C.V.

Tijuana, Baja California

Hace una hora

Compartir:

Correo de contacto

*****@napsmexico.com

Giro

Maquiladora (Export.)

Actividad principal

Administración de maquiladoras.

Número de empleados

10000

Sitio Web corporativo

Datos de sucursal

*****@napsmexico.com

Vía Rápida Poniente 16955-58 Río Tijuana, 3ra. Etapa Tijuana, Baja California

Descripción y detalle de las actividades

Company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age and this is where you come in.

Digital Design Engineer for Mixed-Signals IPs, ASICs and Chipsets used in power solutions. IPs include telemetry ADCs, 100W+ charging (Quick Charge 5.0), 5G power (mmW, envelope tracking, high performance low noise oscillators etc…) and high efficiency power management (DC-DC charge pumps, bucks and linear regulators).

Work includes partnering with international teams in all stages of development from system definition to high-volume (100M+) OEM launches.

Successful applicants will be responsible for participating in, or leading, the design of state-of-the-art Mixed-Signals ASICs in advanced digital deep sub-micron CMOS processes for multi-function mobile platforms.

Responsibilities will include all, or some, of the following:

  • Micro-architecture of chipset, chip and IP-level designs (designs include firmware, RTL and analog hard macros)
  • Negotiating and executing System specification and requirements
  • Actively involved in all aspects of the front-end design from Architecture definition/RTL development/Simulation/Synthesis/DFT Insertion/Static Timing closure and closely work with the Place and Route function.
  • Document ASIC development, hold detailed design reviews with cross-functional teams, generate and maintain design schedules.

Experiencia y requisitos

Preferred Qualifications

  • MS+2 Years ASIC design, verification, or related work experience
  • Applicants should have sound digital design principles with exposure to Front-end Digital design tools – HDL, RTL Linting, CDC, Synthesis, BIST/SCAN insertion, STA.
  • Strong communication and organizational skills
  • Strong process-oriented mindset.

Location: Santa Fé, Tijuana

Beneficios

  • Beneficios de acuerdo a la LFT

Número de vacantes 1

Área Electrónica

Contrato Permanente

Modalidad Presencial

Turno Diurno

Jornada Tiempo Completo

Horario
  • Tiempo completo
  • Lunes a viernes

Estudios Carrera con título profesional

Inglés Hablado: Avanzado, Escrito: Avanzado

Disponibilidad p. viajar No