36 empleos en Tijuana, Baja California de Electrónica

Silicon Test Developer Engineer (Semiconductors)

North American Production Sharing de México, S.A. de C.V.

Minimum Qualifications: • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Preferred Qualifications Master’s Degree in Electrical, Electronics, Mecatronica, Computer Science or related fields. Experience with circuit design (e.g., digital, analog, RF), hardware engineering and hardware design (schematic capture and circuit simulation) or related fields. >1 year of experience in product development, test validation and high-volume production activities related to System on Chip (SOC) - Compute, Data Center, Mobile, Automotive, IoT areas. VLSI technologies – Digital Design, CPU architecture and organization and Semiconductor process. Domain knowledge in one or more of these areas is a plus: CPU, Logic Test (ATPG), Memory, (SRAM, DRAM interfaces), High Speed Serdes, Sensor validation and its corresponding test methodologies. CMOS Analog, and Mixed-Signal circuits such as ADC, DAC, PLL, LDO, LNA, Mixers, Power Amplifiers, and their performance measurements. Experience handling measurement test equipment (oscilloscope, signal generator, spectrum analyzer, time interval analyzer, logic analyzer, network analyzer, ATE, Rohde & Schwarz). Experience with Python/C++/Java/Assembly/Embedded SW. Design for test (DFT) techniques and structural tests such as Scan/ATPG, JTAG and memory BIST is a plus. Hands on experience with data analysis software (JMP, National Instruments, Exensio, etc.) is a plus. Experience with Automated Test Equipment: Advantest or Teradyne is a plus. Familiarity with ARM, Arduino, Microcontroller architecture is a plus. and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc. 2+ years’ experience utilizing schematic capture and circuit simulation software.

Mayo 29 2026 en Tijuana

Entry Level ASIC static timing analysis Engineer (Semiconductors)

North American Production Sharing de México, S.A. de C.V.

Key Qualifications: As an ASIC Timing Engineer, you will play a vital role in Timing analysis targeting the Mobile, Compute, Automotive, and IOT markets. You will be working with physical design team (inside and with other outside company/vendor) on timing closure, CAD teams, IP teams, and Design Technology Teams for flow scripts/tools development and validation. You will facilitate and drive STA methodology for the company using Primetime, Tempus, and best-in-class timing ECO tools. Knowledge of industry STA tools in depth is key to this role. A timing Engineer should be able to understand all kinds of intricate timing paths (digital, analog, mixed signal), timing constraints, and provide solutions if required. Good understanding of RTL to GDS digital flow is required. Familiarity with all areas of timing closure of high-performance, mixed-signal SoCs in sophisticated process technology nodes (40nm to 3nm). Have good Physical Design execution knowledge (Synthesis to timing Sign-off). Good knowledge of low-power techniques, including clock gating, power gating, and multi-voltage designs, is required. Good programming skills in Python, Perl, TCL, Unix shell. Expertise is required for the development of scripted automation for data processing (related to timing convergence). Ability to work and coordinate with large design teams is a MUST. Timing sign-off experience is a plus. IP design experience is a plus. Excellent communication skills. Excellent multitasking skills. Above all, you should be a good team player with the ability to remain calm in challenging technical discussions, demanding customers, and schedule pressure.

Mayo 29 2026 en Tijuana

Software Engineer - AI Solution Enablement Engineer (Semiconductors)

North American Production Sharing de México, S.A. de C.V.

Minimum Qualifications 2+ years of academic or work experience with Programming Language such as C, C++, Java, Python, etc. Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Software Engineering or related work experience. Proven experience working with engineering workflows, developer tools, or internal platforms in large or complex engineering organizations. Hands‑on experience building, enabling, or operationalizing AI‑powered or agent‑based solutions, such as workflows, assistants, or automation systems. Demonstrated ability to translate complex technical capabilities into clear, reusable patterns, templates, and guidance that others can adopt independently. Strong communication and collaboration skills, with experience training, enabling, or influencing engineers across multiple teams and disciplines. Preferred Qualifications Master's degree in Engineering, Information Systems, Computer Science, or related field and 1+ year of Software Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field. Experience with agent frameworks, AI orchestration, or workflow automation platforms in an enterprise setting. Familiarity with enterprise AI platforms, internal developer tooling, and AI governance or enablement models. Experience designing, delivering, or scaling technical training programs, workshops, or certification initiatives. Background in platform enablement, developer productivity, or technology adoption roles, especially in cross‑team environments. Location: Santa Fé, Tijuana

Mayo 29 2026 en Tijuana

Physical Verification Engineer (Semiconductors)

North American Production Sharing de México, S.A. de C.V.

Minimum 2 years of experience in a hands-on PDK role. Expertise in Calibre/ICV/Pegasus runset coding for DRC/LVS/ERC/PERC/MPT/ESD/Latch-up/Antenna, etc. Experience with developing and customization of the StarRC/Calibre-xACT/QRC parasitic extraction flows. As a member of the Physical Verification CAD team, you will maintain and improve all aspects of physical verification flow and methodology. Code custom checks such as Layout/Programmable ERCs, addition of custom devices in LVS, implementation of custom design rules (DRCs), etc., to meet design team requirements. You will need to have a deep understanding of design rule checks (DRC) and layout versus schematic (LVS) runsets, writing from scratch and/or modifying existing ones. Proficiency in integration and tech setup of Calibre LVS with StarRC/QRC and other extraction tools. Utilizing your hands-on skills to revamp/rewrite and streamline the PEX flow. Understanding of Digital/Custom/Analog requirements for various post layout electrical flows. Develop custom extraction solutions for transistor level for design team requirements. Hands-on experience with Field solvers and RC reduction tools. Support design teams with solving their PEX challenges. Support the design teams with solving their PV challenges to facilitate the IP release and chip tapeouts. Collaborate with tool vendors and foundries for tools and flow improvements. Knowledge of deep sub-micron FINFET, Planar, SOI and PMIC process technologies and mask layout design. Proficiency in one or more of the programming/scripting languages – SKILL, Python, Unix, Perl and TCL. Good communication skills and ability to work collaboratively in a team environment. Educational Requirements Required: Bachelor's, Electrical Engineering (with Master’s preferred).

Mayo 29 2026 en Tijuana

Failure Analysis Engineer (Semiconductors)

North American Production Sharing de México, S.A. de C.V.

Required Skills & Qualifications Fast learner with the ability to work independently. Strong understanding of: Semiconductor physics. Device behavior and circuit analysis. Wafer fabrication processes. Proficiency in electrical and physical FA techniques such as: Mechanical polishing, chemical etching. SEM/EDX, curve trace. Thermal emission, photon emission, OBIRCH/TIVA. Familiarity with tester‑interface optical techniques: Soft Defect Localization. Laser Voltage Probing. Frequency mapping. Time‑resolved emission. Experience with SEM nano‑probing (EBIC, EBAC, EBIRCH) on planar, SOI, or FinFET technologies. Knowledge of SCAN, Memory BIST, RF/Analog circuits. Understanding of reliability tests: CDM, HBM, TLP, HTOL, BHAST, Burn‑In, etc. Strong communication, organization, and project management skills. Ability to work in a laboratory environment. Willingness to work flexible hours, including weekend or night shifts. Experience with scripting/programming (Python, automation scripts, Power BI, etc.). Minimum Qualifications Bachelor’s degree in Electrical Engineering, Microelectronics, Physics, or related field. 0–2 years of hands‑on semiconductor failure analysis or physical/chemical lab experience. Preferred Qualifications Master’s degree in Electrical Engineering, Microelectronics, Physics, or related field. 2+ years experience in chip‑level failure analysis. Skills in: Automated Test Equipment (ATE). Data analysis. Product reliability and development

Mayo 29 2026 en Tijuana

No hay más resultados. Ir arriba