ASIC DRAM Bus and PDN Designer - Foránea
North American Production Sharing de México, S.A. de C.V.
Desired Skillset/Experience: Experience with 2.5D and 3D STCO and pathfinding. 2.5 and 3D Chip partition and dependencies on Product KPI like performance, power, chip and beachfront area, chip-chip communication metrics, power grid, etc. System and/or chip-level architecture and physical design experience for 3D cache partitioning (a plus). Physical design experience with SoIC and/or CoWoS. Experience with 2.5D/3D IC design flow and PDK development. Familiarity with heterogeneous integration processes such as hybrid bonding, wafer bonding, TSV, backside metallization. Process development and/or system and product development experience with advanced technology (sub 4nm) and its PPAC assessment. Custom layout, svrf, scripting skills. Hands-on experience with DRC, LVS, PEX (a plus). Ability to work across teams and BUs. Ability to work without supervision and as part of a team. Most tasks do not have defined steps; simultaneous use of multiple mental abilities is generally required to determine the best approach. Advanced data analysis and interpretation skills are required. Education: Bachelor's degree in science, Engineering, or related field and 5+ years of AI relevant System and technology or related work experience. OR master's degree in science, Engineering, or related field and 4+ years of AI relevant System and technology or related work experience. OR PhD in Science, Engineering, or related field and 3+ years of AI relevant System and technology or related work experience.
Enero 19 2026 en Tijuana
